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  <body><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h1 class="register-section">EDSCR2, External Debug Status and Control Register 2</h1><p>The EDSCR2 characteristics are:</p><h2>Purpose</h2>
        <p>Main control register 2 for the debug implementation.</p>
      <h2>Configuration</h2><p>External register EDSCR2 bits [31:0] are architecturally mapped to AArch64 System register <a href="AArch64-mdscr_el1.html">MDSCR_EL1[63:32]</a>.</p><p>EDSCR2 is in the Core power domain.
    </p><p>This register is present only when FEAT_Debugv8p9 is implemented or FEAT_TRBE_EXT is implemented. Otherwise, direct accesses to EDSCR2 are <span class="arm-defined-word">RES0</span>.</p><h2>Attributes</h2>
        <p>EDSCR2 is a 32-bit register.</p>
      <h2>Field descriptions</h2><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="lr" colspan="28"><a href="#fieldset_0-31_4">RES0</a></td><td class="lr" colspan="1"><a href="#fieldset_0-3_3-1">EHBWE</a></td><td class="lr" colspan="1"><a href="#fieldset_0-2_2">RES0</a></td><td class="lr" colspan="1"><a href="#fieldset_0-1_1-1">TTA</a></td><td class="lr" colspan="1"><a href="#fieldset_0-0_0">RES0</a></td></tr></tbody></table><h4 id="fieldset_0-31_4">Bits [31:4]</h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-3_3-1">EHBWE, bit [3]<span class="condition"><br/>When FEAT_Debugv8p9 is implemented:
                        </span></h4><div class="field">
      <p>Extended Halting Breakpoint and Watchpoint Enable. Enables use of additional breakpoints or watchpoints.</p>
    <table class="valuetable"><tr><th>EHBWE</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>Halting disabled for Breakpoint and Watchpoint debug events generated by each breakpoint &lt;n&gt; and Watchpoint &lt;n&gt;, where n is greater than or equal to 16.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>Breakpoints and Watchpoint debug events are not affected by this mechanism.</p>
        </td></tr></table><p>When <a href="AArch64-oslsr_el1.html">OSLSR_EL1</a>.OSLK is 1, this field can be read and written through the <a href="AArch64-mdscr_el1.html">MDSCR_EL1</a> System register.</p>
<p>It is <span class="arm-defined-word">IMPLEMENTATION DEFINED</span> whether this field is implemented or is <span class="arm-defined-word">RES0</span> when 16 or fewer breakpoints are implemented, 16 or fewer watchpoints are implemented, and MDSELR_EL1 is implemented as RAZ/WI.</p><p>The reset behavior of this field is:</p><ul><li>On a Cold reset, 
      this field resets
       to <span class="binarynumber">0</span>.
</li></ul></div><h4 id="fieldset_0-3_3-2"><span class="condition"><br/>Otherwise:
                        </span></h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-2_2">Bit [2]</h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-1_1-1">TTA, bit [1]<span class="condition"><br/>When FEAT_TRBE_EXT is implemented or FEAT_ETEv1p3 is implemented:
                        </span></h4><div class="field"><p>Trap Trace Accesses.</p>
<p>Traps access to the following System registers:</p>
<p>AArch64: <a href="AArch64-trbbaser_el1.html">TRBBASER_EL1</a>, <a href="AArch64-trblimitr_el1.html">TRBLIMITR_EL1</a>, <a href="AArch64-trbmar_el1.html">TRBMAR_EL1</a>, <a href="AArch64-trbmpam_el1.html">TRBMPAM_EL1</a>, <a href="AArch64-trbptr_el1.html">TRBPTR_EL1</a>, <a href="AArch64-trbsr_el1.html">TRBSR_EL1</a>, <a href="AArch64-trbtrg_el1.html">TRBTRG_EL1</a>, <a href="AArch64-trcacatrn.html">TRCACATR&lt;n&gt;</a>, <a href="AArch64-trcacvrn.html">TRCACVR&lt;n&gt;</a>, <a href="AArch64-trcauthstatus.html">TRCAUTHSTATUS</a>, <a href="AArch64-trcauxctlr.html">TRCAUXCTLR</a>, <a href="AArch64-trcbbctlr.html">TRCBBCTLR</a>, <a href="AArch64-trcccctlr.html">TRCCCCTLR</a>, <a href="AArch64-trccidcctlr0.html">TRCCIDCCTLR0</a>, <a href="AArch64-trccidcctlr1.html">TRCCIDCCTLR1</a>, <a href="AArch64-trccidcvrn.html">TRCCIDCVR&lt;n&gt;</a>, <a href="AArch64-trcclaimclr.html">TRCCLAIMCLR</a>, <a href="AArch64-trcclaimset.html">TRCCLAIMSET</a>, <a href="AArch64-trccntctlrn.html">TRCCNTCTLR&lt;n&gt;</a>, <a href="AArch64-trccntrldvrn.html">TRCCNTRLDVR&lt;n&gt;</a>, <a href="AArch64-trccntvrn.html">TRCCNTVR&lt;n&gt;</a>, <a href="AArch64-trcconfigr.html">TRCCONFIGR</a>, <a href="AArch64-trcdevarch.html">TRCDEVARCH</a>, <a href="AArch64-trcdevid.html">TRCDEVID</a>, <a href="AArch64-trceventctl0r.html">TRCEVENTCTL0R</a>, <a href="AArch64-trceventctl1r.html">TRCEVENTCTL1R</a>, <a href="AArch64-trcextinselrn.html">TRCEXTINSELR&lt;n&gt;</a>, <a href="AArch64-trcidr0.html">TRCIDR0</a>, <a href="AArch64-trcidr1.html">TRCIDR1</a>, <a href="AArch64-trcidr2.html">TRCIDR2</a>, <a href="AArch64-trcidr3.html">TRCIDR3</a>, <a href="AArch64-trcidr4.html">TRCIDR4</a>, <a href="AArch64-trcidr5.html">TRCIDR5</a>, <a href="AArch64-trcidr6.html">TRCIDR6</a>, <a href="AArch64-trcidr7.html">TRCIDR7</a>, <a href="AArch64-trcidr8.html">TRCIDR8</a>, <a href="AArch64-trcidr9.html">TRCIDR9</a>, <a href="AArch64-trcidr10.html">TRCIDR10</a>, <a href="AArch64-trcidr11.html">TRCIDR11</a>, <a href="AArch64-trcidr12.html">TRCIDR12</a>, <a href="AArch64-trcidr13.html">TRCIDR13</a>, <a href="AArch64-trcimspec0.html">TRCIMSPEC0</a>, <a href="AArch64-trcimspecn.html">TRCIMSPEC&lt;n&gt;</a>, <a href="AArch64-trciteedcr.html">TRCITEEDCR</a>, <a href="AArch64-trcoslsr.html">TRCOSLSR</a>, <a href="AArch64-trcprgctlr.html">TRCPRGCTLR</a>, <a href="AArch64-trcqctlr.html">TRCQCTLR</a>, <a href="AArch64-trcrsctlrn.html">TRCRSCTLR&lt;n&gt;</a>, <a href="AArch64-trcrsr.html">TRCRSR</a>, <a href="AArch64-trcseqevrn.html">TRCSEQEVR&lt;n&gt;</a>, <a href="AArch64-trcseqrstevr.html">TRCSEQRSTEVR</a>, <a href="AArch64-trcseqstr.html">TRCSEQSTR</a>, <a href="AArch64-trcssccrn.html">TRCSSCCR&lt;n&gt;</a>, <a href="AArch64-trcsscsrn.html">TRCSSCSR&lt;n&gt;</a>, <a href="AArch64-trcsspcicrn.html">TRCSSPCICR&lt;n&gt;</a>, <a href="AArch64-trcstallctlr.html">TRCSTALLCTLR</a>, <a href="AArch64-trcstatr.html">TRCSTATR</a>, <a href="AArch64-trcsyncpr.html">TRCSYNCPR</a>, <a href="AArch64-trctraceidr.html">TRCTRACEIDR</a>, <a href="AArch64-trctsctlr.html">TRCTSCTLR</a>, <a href="AArch64-trcvictlr.html">TRCVICTLR</a>, <a href="AArch64-trcviiectlr.html">TRCVIIECTLR</a>, <a href="AArch64-trcvipcssctlr.html">TRCVIPCSSCTLR</a>, <a href="AArch64-trcvissctlr.html">TRCVISSCTLR</a>, <a href="AArch64-trcvmidcctlr0.html">TRCVMIDCCTLR0</a>, <a href="AArch64-trcvmidcctlr1.html">TRCVMIDCCTLR1</a>, and <a href="AArch64-trcvmidcvrn.html">TRCVMIDCVR&lt;n&gt;</a>.</p><table class="valuetable"><tr><th>TTA</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>Accesses to trace System registers do not generate a Software Access debug event.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>Accesses to trace System registers generate a Software Access debug event, if <a href="AArch64-oslsr_el1.html">OSLSR_EL1</a>.OSLK is 0 and if halting is allowed.</p>
        </td></tr></table>
      <p>When <a href="AArch64-oslsr_el1.html">OSLSR_EL1</a>.OSLK is 1, this field can be read and written through the <a href="AArch64-mdscr_el1.html">MDSCR_EL1</a> System register.</p>
    <p>The reset behavior of this field is:</p><ul><li>On a Cold reset, 
      this field resets
       to <span class="binarynumber">0</span>.
</li></ul></div><h4 id="fieldset_0-1_1-2"><span class="condition"><br/>Otherwise:
                        </span></h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-0_0">Bit [0]</h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h2>Accessing EDSCR2</h2><h4>EDSCR2 can be accessed through the external debug interface:</h4><table class="info"><tr><th>Component</th><th>Offset</th><th>Instance</th></tr><tr><td>Debug</td><td><span class="hexnumber">0x028</span></td><td>EDSCR2</td></tr></table><p>This interface is accessible as follows:</p><ul><li>When DoubleLockStatus(), or !IsCorePowered() or OSLockStatus(), accesses to this register generate an error response.
          </li><li>Otherwise, accesses to this register are <span class="access_level">RW</span>.
          </li></ul><hr class="bottom_line"/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">30/03/2023 19:06; 997dd0cf3258cacf72aa7cf7a885f19a4758c3af</p><p class="copyconf">Copyright © 2010-2023 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.</p></body>
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